1. Field of the invention
The present invention relates to improvement of the internal processings in debugging microprocessors, and more specifically to improvement of the processings in debugging microprocessors at the time of a debugging interrupt.
2. Description of related art
Hitherto, as a tool for development of systems and programs, a so-called "in-circuit emulator" has been widely used. This in-circuit emulator is ordinarily made such that an operation mode transfer from the execution of a user's program (called the "emulation mode" hereinafter) to the execution of a supervisor interrupt program (called the "monitor mode" hereinafter) is performed by the supervisor interrupt to an emulation microprocessor. Further, the transfer from monitor mode to emulation mode is performed by a return instruction.
Here, referring to FIG. 1, there is diagrammatically shown the construction of a typical, conventional debugging processor generally used as the above mentioned emulation microprocessor. The shown debugging processor generally indicated by Reference Numeral 10 includes, similarly to ordinary processors (CPUs), an arithmetic logic unit (ALU) 12, a data bus controller 14, a register group 16 including a stack pointer (SP) area therein, and an instruction register 18, which are coupled to an internal bus 20. The register group 16 is also coupled through an address path 22 to an address controller 24. To the internal bus 22 an emulation program counter (PC) 26 is also coupled, which is in turn coupled to the address controller 24 through a program counter (PC) path 28. The instruction register 18 is coupled to an instruction decode/CPU controller 30. Furthermore, the data bus controller 14 is coupled to an data bus 32, and the address controller 24 is coupled to an address bus 34. The instruction decoder/CPU controller 30 is coupled to a control bus 36. Through this control bus 36, there are supplied various control signals including a status signal, a read signal and a write signal for a memory, and also, a supervisor interrupt signal and an acknowledge signal in resonse thereto, etc.
When the above mentioned debugging microprocessor acknowledges the supervisor interrupt request signal, the debugging microprocessor generates an acknowledge signal and moves into a monitor mode. At this time, in order to preserve the status of various elements when the emulation is stopped, it is necessary to save the contents of the emulation PC 26, a program status word (PSW) in the register group 16 and the like, to a stack area within a memory managed by a monitor. The reason for this is that the PC, PSW and others used in the emulation mode are also used in the monitor mode for execution of a given program, and therefore, if the contents of the PC, PSW and others were not preserved, the status at the time of the emulation mode stop becomes unknown, namely it becomes impossible to restart the emulation mode in response to a return instruction. Furthermore, if the saved data of the PC, PSW and others are modified, it is possible to restart the emulation mode from any desired condition.
The following is one example of a sequence for going to an interrupt operation in the above mentioned conventional debugging microprocessor.
______________________________________ (a) (SP-1) .rarw. PSW (SP-2) .rarw. PC SP .rarw. SP-2 PC .rarw. INTERRUPT VECTOR (b) PC .rarw. (SP) PSW .rarw. (SP + 1) SP .rarw. (SP + 2) (c) EMUL: BRKRET INT1: CMP ACC, 0H JR NZ, EMUL . . . ______________________________________
Namely, the contents of PSW and PC are saved in a stack area in the memory designated by the SP, and it goes to the monitor of the address indicated by a supervisor interrupt vector. In the case of executing an instruction for returning from the monitor mode to the emulation mode, the data of the stack is returned to the PC and PSW as shown in the above (b), and then the emulation mode is restarted.
In general, the in-circuit emulator is such that all the memory space of the microprocessor is made open to the user in the course of the emulation mode and on the other hand all the contents of the user's memory must be preserved in the course of the monitor mode. Therefore, the debugging microprocessor is ordinarily switched to access the user's memory in the course of the emulation mode and the debug memory in the course of the monitor mode.
In the conventional debugging microprocessor 10 as mentioned above, therefore, when the mode is transferred from the emulation mode to the monitor mode by the supervisor interrupt, the contents of the PC, PSW and others are saved in a memory area designated by the SP. In addition, the in-circuit emulator switches the memory from the user's memory to the debug memory in response to a supervisor interrupt acknowledge signal. At this time, however, since the SP of the debugging microprocessor has assumed any unknown value in the process of the emulation mode, it is impossible to know where a stack area is formed within the debug memory. Therefore, it is necessary to forcibly set a save area in a predetermined area. Namely, the SP address is outputted from the address bus of the debugging microprocessor into the debug memory at the time of saving, but the control must be performed in such a manner that this address is not actually supplied to the debug memory, and an substituted address indicative of a predetermined save area is supplied to the debug memory.
Similarly, when the mode is switched from the monitor mode to the emulation mode by a return instruction as a result of the supervisor interrupt processing, the address must be switched so as to return the content of the save area of the debug memory to the PC, PSW and others so that the emulation mode can be restarted.
FIG. 2 diagrammatically illustrates a save address control section provided in a conventional in-circuit emulator which uses the conventional debugging microprocessor.
The shown save address control section of the in-circuit emulator includes the debugging microprocessor 10 and a user's memory 40 coupled through the address bus 34 to the debugging microprocessor 10. To the address bus 34, there is also coupled an address selector 42, which is in turn coupled to receive a save address from a save address generator 44. An output of the address selector 42 is coupled to a debug memory 46. The shown save address control section further includes a timing controller 48 coupled to the control bus 36 to receive the control signal from the debugging microprocessor 10. This timing controller 48 outputs an address control signal to the save address generator 44 and also an ENABLE signal to the debug memory 46. This ENABLE signal is inverted by an inverter 50 and the inverted ENABLE signal is applied to the user's memory 40. Further, the timing controller 48 generates a select signal for controlling the address selector 42.
In the above mentioned address control section, if the timing controller 48 detects the supervisor interrupt acknowledge signal, the controller 48 generates the select signal supplied to the address selector 42 so that the save address generated by the save address generator 44 is supplied through the address selector 42 to the debug memory 46. Furthermore, the timing controller 48 activates the ENABLE signal to the debug memory 46 so that the debug memory 46 is enabled. On the other hand, since the inverted ENABLE signal is inputted to the user's memory 40, the user's memory 40 is disabled.
If the save operation is started, the timing controller 48 generates the address control signal supplied to the save address generator 44 to cause the save address generator 44 to decrement the save address signal, so that the contents of the PC, PSW and others are sequentially saved in a memory area designated by the decrementing save address signal. After the save operator has been completed, the timing controller 48 controls the address selector 42 so that the address on the address bus 34 is supplied to the debug memory 46. In addition, at the time of executing the return instruction, the save address generated by the save address generator 44 is supplied to the debug memory 46 so that the contents of the designated areas in the debug memory 46 are returned to the PC, PSW and others. Thereafter, the execution of the program of the user's memory is restarted. In other words, the emulation mode is restarted.
As seen from the above, if the in-circuit emulator uses the debugging microprocessor 10 shown in FIG. 1, the address selector 42, the save address generator 44 and the timing controller 48 are indispensable to the save address control section, and therefore, the supervisor interrupt control is very complicated.
In addition, in the case that the in-circuit emulator executes an emulation operation in which the emulation mode is stopped when an accumulator becomes "0", a supervisor interrupt signal is generated for the debugging microprocessor at every time occurrence of each instruction. Accordingly, as the steps (a).fwdarw.(c).fwdarw.(b) as mentioned above, the save of the contents of the PC, PSW and others, the check of the content of the accumulator and the return of the saved contents of the PC, PSW and others must be executed at every time occurrence of each instruction. As a result, the execution speed of the emulation mode is very much reduced.